Gate Space

Really we shouldn't be talking about List-Space as the bottom level because clearly, a linked list is still quite a specific and complicated structure, requiring some kind of execution environment. The next level down is to look at the system in terms of logic-gates. It turns out that all gates can be made from just NAND gates or just NOR gates since they both exhibit functional completeness. This layer is not well known by The Project yet, we plan on using Node-Space to build a suitable environment for mapping the lower levels, in fact, even List-Space doesn't actually need to be programmed as the current language environments already have efficiently implemented structures which we can use to build Node-Space directly.

Although the specifics os this layer are still in development, the general idea is that Gate-Space is a space of addressable-NAND-gates, in which a single quantum of energy represents the ability to update a particular address to correctly reflect its output based on its inputs.

A NAND-gate can be thought of as something which exhibits potential for change on its output unless the number of inputs exhibiting potential for change exceeds a defined critical limit. Using this simple model we can build a matrix of gates which exhibit both storage and change.

We can then design this low-level space to allow list-space traversal and nodal-reduction. The reason for continuing to map lower levels even though we can execute Node-Space directly is that we're trying to connect the conceptual structure of Node-Space with the structure of own own space-time/perception method. This direction allows us to study different geometric representations of the low-level space to find highly symmetric, recursive and simple forms which still support the higher layers. Some of these forms should reduce back to nothing by their structural implications, but this is not critical to development.